integrated silicon solution, inc. ? 1-800-379-4774 1 preliminary information rev. 00c 11/30/00 IS62LV25616LL issi ? this document contains preliminary information data. issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated silicon solution, inc. 256k x 16 low voltage, ultra low power cmos static ram features ? high-speed access time: 70 and 85 ns cmos low power operation ? 135 mw (typical) operating ? 16.5 w (typical) cmos standby ttl compatible interface levels single 2.7v-3.3v v cc power supply fully static operation: no clock or refresh required three state outputs data control for upper and lower bytes industrial temperature available available in the 44-pin tsop (type ii) and 48-pin mini bga (8mm x 10mm and 7.2mm x 8.7mm) description the issi IS62LV25616LL is high-speed, 4,194,304 bit static ram organized as 262,144 words by 16 bits. it is fabricated using issi 's high-performance cmos technology. this highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. when ce is high (deselected) or when ce is low and both lb and ub are high, the device assumes a standby mode at which the power dissipation can be reduced down with cmos input levels. easy memory expansion is provided by using chip enable and output enable inputs, ce and oe . the active low write enable ( we ) controls both writing and reading of the memory. a data byte allows upper byte ( ub ) and lower byte ( lb ) access. the IS62LV25616LL is packaged in the jedec standard 44-pin tsop (type ii) and 48-pin mini bga (8mm x 10mm and 7.2mm x 8.7mm). functional block diagram preliminary information november 2000 a0-a17 ce oe we 256k x 16 memory array decoder column i/o control circuit gnd vcc i/o data circuit i/o0-i/o7 lower byte i/o8-i/o15 upper byte ub lb
IS62LV25616LL issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 11/30/00 pin configurations 44-pin tsop (type ii) 48-pin mini bga (8mm x 10mm and 7.2mm x 8.7mm) truth table i/o pin mode we ce oe lb ub i/o0-i/o7 i/o8-i/o15 vcc current not selected x h x x x high-z high-z i sb 1 , i sb 2 x l x h h high-z high-z i sb 1 , i sb 2 x l x h h high-z high-z i sb 1 , i sb 2 output disabled h l h x x high-z high-z i cc read h l l l h d out high-z i cc h l l h l high-z d out hllll d out d out write l l x l h d in high-z i cc l l x h l high-z d in llxll d in d in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 a4 a3 a2 a1 a0 ce i/o0 i/o1 i/o2 i/o3 vcc gnd i/o4 i/o5 i/o6 i/o7 we a16 a15 a14 a13 a12 a5 a6 a7 oe ub lb i/o15 i/o14 i/o13 i/o12 gnd vcc i/o11 i/o10 i/o9 i/o8 nc a8 a9 a10 a11 a17 pin descriptions a0-a17 address inputs i/o0-i/o15 data inputs/outputs ce chip enable input oe output enable input we write enable input lb lower-byte control (i/o0-i/o7) ub upper-byte control (i/o8-i/o15) nc no connection vcc power gnd ground 1 2 3 4 5 6 a b c d e f g h lb oe a0 a1 a2 n/c i/o 8 ub a3 a4 ce i/o 0 i/o 9 i/o 10 a5 a6 i/o 1 i/o 2 gnd i/o 11 a17 a7 i/o 3 vcc vcc i/o 12 nc a16 i/o 4 gnd i/o 14 i/o 13 a14 a15 i/o 5 i/o 6 i/o 15 nc a12 a13 we i/o 7 nc a8 a9 a10 a11 nc
IS62LV25616LL issi ? integrated silicon solution, inc. ? 1-800-379-4774 3 preliminary information rev. 00c 11/30/00 1 2 3 4 5 6 7 8 9 10 11 12 dc electrical characteristics (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage v cc = 3.0v, i oh = ? 1 ma 2.2 ? v v ol output low voltage v cc = 3.0v, i ol = 2.1 ma ? 0.4 v v ih input high voltage 2.2 v cc + 0.2 v v il (1) input low voltage ? 0.2 0.4 v i li input leakage gnd v in v cc ? 11a i lo output leakage gnd v out v cc , outputs disabled ? 11a notes: 1. v il (min.) = ? 2.0v for pulse width less than 10 ns. absolute maximum ratings (1) symbol parameter value unit v term terminal voltage with respect to gnd ? 0.5 to vcc+0.3 v t bias temperature under bias ? 40 to +85 c v cc vcc related to gnd ? 0.3 to +4.0 v t stg storage temperature ? 65 to +150 c p t power dissipation 1.0 w note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operating range range ambient temperature v cc commercial 0 c to +70 c 2.7v - 3.3v industrial ? 40 c to +85 c 2.7v - 3.3v capacitance (1) symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf note: 1. tested initially and after any design or process changes that may affect these parameters.
IS62LV25616LL issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 11/30/00 ac test conditions parameter unit input pulse level 0.4v to 2.2v input rise and fall times 5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads 3070 ? 30 pf including jig and scope 3150 ? output 2.8v figure 1 3070 ? 5 pf including jig and scope 3150 ? output 2.8v figure 2 power supply characteristics (1) (over operating range) -70 -85 symbol parameter test conditions min. max. min. max. unit i cc vcc dynamic operating v cc = max., com. ? 45 ? 40 ma supply current i out = 0 ma, f = f max ind. ? 50 ? 45 i cc 1 operating supply v cc = max., com. ? 5 ? 5ma current i out = 0 ma, f = 0 ind. ? 5 ? 5 i sb 1 ttl standby current v cc = max., com. ? 0.4 ? 0.4 ma (ttl inputs) v in = v ih or v il ind. ? 1.0 ? 1.0 ce v ih , f = 0 or ulb control v cc = max., v in = v ih or v il ce = v il , f = 0, ub = v ih , lb = v ih i sb 2 cmos standby v cc = max., com. ? 5 ? 5a current (cmos inputs) ce v cc ? 0.2v, ind. ? 5 ? 5 v in v cc ? 0.2v, or v in 0.2v, f = 0 or ulb control v cc = max., ce = v il v in 0.2v, f = 0; ub / lb = v cc ? 0.2v note: 1. at f = f max , address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
IS62LV25616LL issi ? integrated silicon solution, inc. ? 1-800-379-4774 5 preliminary information rev. 00c 11/30/00 1 2 3 4 5 6 7 8 9 10 11 12 read cycle switching characteristics (1) (over operating range) -70 -85 symbol parameter min. max. min. max. unit t rc read cycle time 70 ? 85 ? ns t aa address access time ? 70 ? 85 ns t oha output hold time 10 ? 15 ? ns t ace ce access time ? 70 ? 85 ns t doe oe access time ? 35 ? 40 ns t hzoe (2) oe to high-z output ? 25 ? 25 ns t lzoe (2) oe to low-z output 5 ? 5 ? ns t hzce (2) ce to high-z output 0 25 0 25 ns t lzce (2) ce to low-z output 10 ? 10 ? ns t ba lb , ub access time ? 70 ? 85 ns t hzb lb , ub to high-z output 0 25 0 25 ns t lzb lb , ub to low-z output 0 ? 0 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.4 to 2.2v and output loading specified in figure 1. 2. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested.
IS62LV25616LL issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 11/30/00 data valid previous data valid t aa t oha t oha t rc d out address ac waveforms read cycle no. 1 (1,2) (address controlled) ( ce = oe = v il , ub or lb = v il ) t rc t oha t aa t doe t lzoe t ace t lzce t hzoe high-z data valid t hzb address oe ce lb , ub d out t hzce t ba t lzb ac waveforms read cycle no. 2 (1,3) ( ce , oe , and ub / lb controlled) notes: 1. we is high for a read cycle. 2. the device is continuously selected. oe , ce , ub , or lb = v il . 3. address is valid prior to or coincident with ce low transition.
IS62LV25616LL issi ? integrated silicon solution, inc. ? 1-800-379-4774 7 preliminary information rev. 00c 11/30/00 1 2 3 4 5 6 7 8 9 10 11 12 write cycle switching characteristics (1,2) (over operating range) -70 -85 symbol parameter min. max. min. max. unit t wc write cycle time 70 ? 85 ? ns t sce ce to write end 65 ? 70 ? ns t aw address setup time to write end 65 ? 70 ? ns t ha address hold from write end 0 ? 0 ? ns t sa address setup time 0 ? 0 ? ns t pwb lb , ub valid to end of write 60 ? 70 ? ns t pwe we pulse width 55 ? 60 ? ns t sd data setup to write end 30 ? 35 ? ns t hd data hold from write end 0 ? 0 ? ns t hzwe (3) we low to high-z output ? 30 ? 30 ns t lzwe (3) we high to low-z output 5 ? 5 ? ns notes: 1. test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5v, input pulse levels of 0.4v t o 2.2v and output loading specified in figure 1. 2. the internal write time is defined by the overlap of ce low and ub or lb , and we low. all signals must be in valid states to initiate a write, but any one can go inactive to terminate the write. the data input setup and hold timing are referenced to the rising or falling edge of the signal that termi nates the write. 3. tested with the load in figure 2. transition is measured 500 mv from steady-state voltage. not 100% tested. notes: 1. write is an internally generated signal asserted during an overlap of the low states on the ce and we inputs and at least one of the lb and ub inputs being in the low state. 2. write = ( ce ) [ ( lb ) = ( ub ) ] ( we ). ac waveforms write cycle no. 1 (1,2) ( ce controlled, oe = high or low) data undefined t wc valid address t scs t pwe1 t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in data in valid t lzwe t sd ub_cswr1.eps
IS62LV25616LL issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 11/30/00 write cycle no. 2 ( we controlled: oe is high during write cycle) data undefined low t wc valid address t pwe1 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cswr2.eps write cycle no. 3 ( we controlled: oe is low during write cycle) data undefined t wc valid address low low t pwe2 t aw t ha high-z t pbw t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd ub_cswr3.eps
IS62LV25616LL issi ? integrated silicon solution, inc. ? 1-800-379-4774 9 preliminary information rev. 00c 11/30/00 1 2 3 4 5 6 7 8 9 10 11 12 data retention switching characteristics symbol parameter test condition min. max. unit v dr vcc for data retention see data retention waveform 1.5 3.3 v i dr data retention current vcc = 2.0v, ce vcc ? 0.2v ? 5a t sdr data retention setup time see data retention waveform 0 ? ns t rdr recovery time see data retention waveform t rc ? ns data retention waveform ( ce controlled) v cc ce v cc e 0.2v t sdr t rdr v dr ce gnd 2.7v 2.0v data retention mode write cycle no. 4 ( ub / lb controlled) data undefined t wc address 1 address 2 t wc high-z t pbw word 1 low word 2 t hd t sa t hzwe address ce ub , lb we d out d in oe data in valid t lzwe t sd t pbw data in valid t sd t hd t sa t ha t ha ub_cswr4.eps
IS62LV25616LL issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 preliminary information rev. 00c 11/30/00 issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to +70 c speed (ns) order part no. package 70 IS62LV25616LL-70t t sop (type ii) IS62LV25616LL-70b m ini bga (8mm x 10mm) IS62LV25616LL-70m m ini bga (7.2mm x 8.7mm) 85 IS62LV25616LL-85t t sop (type ii) IS62LV25616LL-85b m ini bga (8mm x 10mm) IS62LV25616LL-85m m ini bga (7.2mm x 8.7mm) industrial range: ? 40 c to +85 c speed (ns) order part no. package 70 IS62LV25616LL-70ti tsop (type ii) IS62LV25616LL-70bi m ini bga (8mm x 10mm) IS62LV25616LL-70mi m ini bga (7.2mm x 8.7mm) 85 IS62LV25616LL-85ti tsop (type ii) IS62LV25616LL-85bi m ini bga (8mm x 10mm) IS62LV25616LL-85mi m ini bga (7.2mm x 8.7mm)
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